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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT126 Quad buffer/line driver; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Quad buffer/line driver; 3-state FEATURES * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION 74HC/HCT126 The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The HC/HCT126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a HIGH impedance OFF-state. The "126" is identical to the "125" but has active HIGH enable inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V (CL x VCC2 x fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nA to nY input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 9 3.5 23 11 3.5 24 HCT ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification Quad buffer/line driver; 3-state PIN DESCRIPTION PIN NO. 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBOL 1OE to 4OE 1A to 4A 1Y to 4Y GND VCC NAME AND FUNCTION output enable inputs (active HIGH) data inputs data outputs ground (0 V) positive supply voltage 74HC/HCT126 (a) (b) Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS nOE H H L Note 1. H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram (one buffer). nA L H X OUTPUT nY L H Z December 1990 3 Philips Semiconductors Product specification Quad buffer/line driver; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay nA to nY typ. 30 11 9 tPZH/ tPZL 3-state output enable time nOE to nY 3-state output disable time nOE to nY output transition time 41 15 12 41 15 12 14 5 4 max. 100 20 17 125 25 21 125 25 21 60 12 10 -40 to +85 min. max. 125 25 21 155 31 26 155 31 26 75 15 13 -40 to +125 min. max. 150 30 26 190 38 32 190 38 32 90 18 15 ns ns ns ns UNIT 74HC/HCT126 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 Fig.7 Fig.7 Fig.6 tPHZ/ tPLZ tTHL/ tTLH December 1990 4 Philips Semiconductors Product specification Quad buffer/line driver; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT126 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per unit, multiply this value by the unit load coefficient shown in the table below. INPUT nA, nOE UNIT LOAD COEFFICIENT 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tPZH/ tPZL propagation delay nA to nY 3-state output enable time nOE to nY 3-state output disable time nOE to nY output transition time typ. 14 13 max. 24 25 -40 to +85 min. max. 30 31 -40 to +125 min. max. 36 38 ns ns 4.5 4.5 Fig.6 Fig.7 UNIT VCC WAVEFORMS (V) TEST CONDITIONS tPHZ/ tPLZ 18 28 35 42 ns 4.5 Fig.7 tTHL/ tTLH 5 12 15 18 ns 4.5 Fig.6 December 1990 5 Philips Semiconductors Product specification Quad buffer/line driver; 3-state AC WAVEFORMS 74HC/HCT126 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 6 |
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